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DATA SHEET
MOS INTEGRATED CIRCUIT
PD7554A, 7554A(A)
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The PD7554A is a product of the PD7554, 7564 sub-series which is a 4-bit single-chip microcomputer with a small number of ports in a small package, which is enabled to operate even at the super-low voltage of 2.0 V so that it is optimized for handy-type systems operating with dry cells. The PD7554A is a low-order model in the PD7500 series (PD7554A only). This device incorporates a serial interface, and serves as the sub-CPU for a high-order model of that series or the 8-bit microcomputer. It is optimized for distributed processing of the system. The PD7554A has outputs to directly drive a triac and LEDs and allows selection among many types of input/ output circuits using their respective mask options, sharply reducing the number of external circuits required. Details of functions are described in the User's Manual shown below. Be sure to read in design.
PD7554, 7564 User's Manual: IEM-1111D
FEATURES
* Range of supply voltage 7554A : 2.0 to 6.0 V 7554A(A) : 2.7 to 6.0 V * Drive with two 1.5 V manganese cells * 47 types of instructions (Subset of PD7500H SET B) * Instruction cycle External clock : 2.86 s (in operation at 700 kHz, 5 V) RC oscillation : 4 s (in operation at 500 kHz, 5 V) * Program memory (ROM) capacity: 1024 x 8 bits * Data memory (RAM) capacity: 64 x 4 bits * Test source: One external source and two internal sources * 8-bit timer/event counter * 16 I/O lines (Total output current of all pins: 100 mA) * Can directly drive a triac and a LED: P80 to P83 * Can directly drive LEDs: P100 to P103 and P110 to P113 * Mask option function provided for every port * 8-bit serial interface * Standby (STOP/HALT) function * Low supply voltage data retaining function for data memory * Built-in ceramic oscillator for system clock RC Oscillation with an external resistor R (Incorporating capacitor C)
5
APPLICATION
PD7554A : Sub-CPU including handy-type system, PPC, printer, VCR, audio equipments, etc. PD7554A(A) : Automotive and transportation equipments, etc.
The quality level and absolute maximum ratings of the PD7554A and the PD7554A(A) differ. Except where specifically noted, explanations here concern the PD7554A as a representative product. If you are using the PD7554A(A), use the information presented here after checking the functional differences.
5
The information in this document is subject to change without notice.
Document No. IC-2419C (O. D. No. IC-7835C) Date Published January 1995 P Printed in Japan
The mark 5 shows major revised points.
(c)
1994 1989
PD7554A, 7554A(A)
ORDERING INFORMATION
Ordering Code Package 20-pin plastic shrink DIP (300 mil) 20-pin plastic SOP (300 mil) 20-pin plastic shrink DIP (300 mil) 20-pin plastic SOP (300 mil) Quality Grade Standard Standard Special Special
5 5
PD7554ACS-xxx PD7554AG-xxx PD7554ACS(A)-xxx PD7554AG(A)-xxx
Caution Be sure to specify a mask option when ordering this device. Remarks "xxx" is a ROM code number.
Please rfer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
PIN CONFIGURATION (TOP VIEW)
P00/INT0 P01/SCK P02/SO P03/SI P80 P81 P82 CL2(P83) CL1 VDD
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VSS P113 P112 P111 P110 P103 P102 P101 P100 RESET
PD7554A
2
BLOCK DIAGRAM OF PD7554A
P01/SCK INT0
P03/SI
P02/SO
P00/INT0
CLOCK CONTROL CL
CP
TIMER/EVENT COUNTER
TEST CONTROL
SERIAL INTERFACE
PROGRAM COUNTER (10)
ALU
C
A (4)
PORT0 BUFFER
4
P00-P03
GENERAL REGISTERS H (2) PROGRAM MEMORY 1024 x 8 BITS INSTRUCTION DECODER STACK POINTER (6) L (2)
PORT8 LATCH BUFFER
3
P80-P82 P83 (CL2)
PORT10 LATCH BUFFER CL
4
P100-P103
DATA MEMORY
SYSTEM CLOCK GENERATOR
STANDBY CONTROL
64 x 4 BITS
PORT11 LATCH BUFFER
PD7554A, 7554A(A)
4
P110-P113
CL1 CL2(P83)
VDD
VSS
RESET
3
PD7554A, 7554A(A)
CONTENTS 1. PIN FUNCTIONS ........................................................................................................................................... 6
1.1 1.2 1.3 1.4 1.5 1.6 1.7 PORT FUNCTIONS ................................................................................................................................................. 6 OTHER THAN PORTS ............................................................................................................................................ 6 PIN MASK OPTION ................................................................................................................................................ 7 CAUTION ON USE OF P00/INT0 PIN AND RESET PIN ..................................................................................... 8 PIN INPUT/OUTPUT CIRCUITS ............................................................................................................................ 9 RECOMMENDED CONNECTION OF UNUSED PD7554A PINS .................................................................... 12 OPERATION OF INPUT/OUTPUT PORTS .......................................................................................................... 13
2. INTERNAL BLOCK FUNCTIONS ............................................................................................................... 15
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 PROGRAM COUNTER (PC): 10 BITS .................................................................................................................. 15 STACK POINTER (SP): 6 BITS ............................................................................................................................ 16 PROGRAM MEMORY (ROM): 1024 WORDS x 8 BITS ..................................................................................... 17 GENERAL REGISTER ........................................................................................................................................... 17 DATA MEMORY (RAM): 64 x 4 BITS ................................................................................................................. 18 ACCUMULATOR (A): 4 BITS ............................................................................................................................... 19 ARITHMETIC LOGIC UNIT (ALU): 4 BITS .......................................................................................................... 19 PROGRAM STATUS WORD (PSW): 4 BITS ...................................................................................................... 19
2.9 SYSTEM CLOCK GENERATOR ........................................................................................................................... 20 2.10 CLOCK CONTROL CIRCUIT ................................................................................................................................. 21 2.11 TIMER/EVENT COUNTER ................................................................................................................................... 22 2.12 SERIAL INTERFACE ............................................................................................................................................. 23 2.13 TEST CONTROL CIRCUIT .................................................................................................................................... 25
3. STANDBY FUNCTIONS .............................................................................................................................. 27
3.1 3.2 3.3 STOP MODE .......................................................................................................................................................... 27 HALT MODE .......................................................................................................................................................... 27 CANCELLING THE STANDBY MODE ................................................................................................................. 28
4. RESET FUNCTIONS .................................................................................................................................... 29
4.1 DETAILS OF INITIALIZATION ............................................................................................................................. 29
5. PD7554A INSTRUCTION SET ............................................................................................................... 30 6. ELECTRICAL SPECIFICATIONS .............................................................................................................. 35 7. CHARACTERISTICS CURVES .................................................................................................................. 47 8. PD7554A APPLIED CIRCUITS ............................................................................................................... 51 9. PACKAGE INFORMATION ....................................................................................................................... 52 10. RECOMMENDED PACKAGING PATTERN OF PLASTIC SOP (REFERENCE) ..................................... 56 11. RECOMMENDED SOLDERING CONDITIONS ....................................................................................... 57
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PD7554A, 7554A(A)
APPENDIX A. COMPARISON BETWEEN SUB-SERIES PRODUCT FUNCTIONS..................................... 58 APPENDIX B. DEVELOPMENT TOOLS ........................................................................................................ 59 APPENDIX C. RELATED DOCUMENTS ........................................................................................................ 61 5
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PD7554A, 7554A(A)
1. PIN FUNCTIONS
1.1 PORT FUNCTIONS
Input/Output Input Input/output Input Output Output Dual-Function Pin INT0 SCK SO SI -- CL2 4-bit output port (Port 8) High current (15 mA), middle-high voltage (9 V) output 4-bit I/O port (Port 10) Middle-high current (10 mA), middle-high voltage (9 V) input/output 4-bit I/O port (Port 11) Middle-high current (10 mA), middle-high voltage (9 V) input/output High impedance 4-bit input port (Port 0) P00 serves also as a count clock (event pulse) input. Input Function After RESET Input/Output Circuit S X W S O
Pin Name P00 P01 P02 P03 P80 to P82 P83
Note
P100 to P103 Input/output
--
P110 to P113 Input/output
--
High impedance or high-level output
P
Note Mask options are available to specify port functions only when the external clock (CL1) is used.
1.2
OTHER THAN PORTS
Input/Output Input Input/output Output Input Dual-Function Pin P00 P01 P02 P03 Function Edge detection testable input pin (Rising edge) Serial clock Input/output pin Serial data output pin Serial data input pin Connection pin for resistor R for RC oscillator When an external clock is used, its input must be connected to CL1, and CL2 can be used as P83 using the mask option. System reset input pin (high-level active) A pull-down resistor can be incorporated using the mask option. Positive power supply pin GND potential pin Input Input Input After RESET Input/Output Circuit S X W S
Pin Name INT0 SCK SO SI CL1 CL2
Q
P83
RESET
R
VDD VSS
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PD7554A, 7554A(A)
1.3 PIN MASK OPTION Each pin is provided with the following mask options which can be selected for each bit according to the purpose:
Pin Name P00 No internally provided resistor Pull-up resistor internally provided No internally provided resistor Pull-up resistor internally provided No internally provided resistor Pull-up resistor internally provided No internally provided resistor Pull-up resistor internally provided N-channel open-drain output N-channel open-drain output N-channel open-drain output Used as CL2 or P83N-ch open-drain output pin. Mask Options Pull-down resistor internally provided
5
P01
Pull-down resistor internally provided
P02
Pull-down resistor internally provided
P03
Pull-down resistor internally provided
P80 P81 P82 P83/CL2 P100
CMOS (push-pull) output CMOS (push-pull) output CMOS (push-pull) output Used as P83 pin (push-pull output).
N-channel open-drain I/O Push-pull I/O N-channel open-drain + I/O with pull-up resistor internally provided N-channel open-drain I/O Push-pull I/O N-channel open-drain + I/O with pull-up resistor internally provided N-channel open-drain I/O Push-pull I/O N-channel open-drain + I/O with pull-up resistor internally provided N-channel open-drain I/O Push-pull I/O N-channel open-drain + I/O with pull-up resistor internally provided N-channel open-drain I/O Push-pull I/O N-channel open-drain + I/O with pull-up resistor internally provided N-channel open-drain I/O Push-pull I/O N-channel open-drain + I/O with pull-up resistor internally provided N-channel open-drain I/O Push-pull I/O N-channel open-drain + I/O with pull-up resistor internally provided N-channel open-drain I/O Push-pull I/O N-channel open-drain + I/O with pull-up resistor internally provided RC oscillation Pull-down resistor is not internally provided External clock Pull-down resistor is internally provided
P101
P102
P103
P110
P111
P112
P113
System clockNote RESET
Note When using RC oscillation, switch the P83/CL2 pin to the CL2 pin. There is no mask option for PROM products. For more information, see the PD75P54 Data Sheet (IC-2830).
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PD7554A, 7554A(A)
1.4
CAUTION ON USE OF P00/INT0 PIN AND RESET PIN
In addition to the functions shown in 1.1, 1.2 and 1.3, the P00/INT0 pin and RESET pin have a function for setting the test mode in which the internal operation of the PD7554A is tested (IC test only). When a potential greater than VSS is applied to either of these pins, the test mode is set. As a result, if noise exceeding VSS is applied during normal operation, the test mode will be entered and normal operation may be impeded. If, for example, the routing of the wiring between the P00/INT0 pin and RESET pin is long, the above problem may occur as the result of inter-wiring noise between these pins. Therefore, wiring should be carried out so as to suppress inter-wiring noise as far as possible. If it is not possible to suppress noise, anti-noise measures should be taken using external parts as shown in the figures below. * Connection of diode with small VF between P00/ INT4/RESET pin and VSS
VDD
* Connection of capacitor between P00/INT0/ RESET pin and VSS
VDD
VDD P00/INT0, RESET Diode with Small VF VSS VSS
VDD P00/INT0, RESET
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PD7554A, 7554A(A)
1.5 PIN INPUT/OUTPUT CIRCUITS This section presents the input/output circuit for each pin of the PD7554A in a partly simplified format: (1) Type A (for Type W)
VDD
P-ch IN
N-ch
Forming an input buffer conformable to the CMOS specification (2) Type D (for Types W and X)
VDD
data
P-ch
OUT
output disable
N-ch
Forming a push-pull output which becomes high impedance (with both P-ch and N-ch off) in response to RESET input
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PD7554A, 7554A(A)
(3) Type O
VDD
data
P-ch
Mask Option OUT output disable N-ch (Middle-High Voltage, High-Current)
(4) Type P
VDD
data
P-ch
Mask Option
OUT
output disable
N-ch (Middle-High Voltage, High-Current)
Middle-High Input Buffer
(5) Type Q
RC Oscillator
CL1 CL2/P83 Mask Option
Type 0
10
PD7554A, 7554A(A)
(6) Type R
Mask Option
(7) Type S
VDD
Mask Option IN
(8) Type W
data Type D output disable VDD IN/OUT
Mask Option Type A
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PD7554A, 7554A(A)
(9) Type X
data Type D output disable VDD IN/OUT
Mask Option
1.6
RECOMMENDED CONNECTION OF UNUSED PD7554A PINS
Pin P00/INT0 P01 to P03 P80 to P82 P100 to P103 P110 to P113 Recommended Connection Connect to VSS. Connect to VSS or VDD. Leave open. Input state : Connect to VSS or VDD. Output state: Leave open.
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PD7554A, 7554A(A)
1.7
OPERATION OF INPUT/OUTPUT PORTS
(1) P00 to P03 (Port 0) The port 0 is a 4-bit input port consisting of 4-bit input pins P00 to P03. In addition to being used for port input, P00 serves as a count clock input or testable input (INT0), each of P01 to P03 serves as a serial interface input/output. To use P00 as a count clock input, set bits 2 (CM2) and 1 (CM1) of the clock mode register to 01. (See 2.10 "CLOCK CONTROL CIRCUIT" for details.) To use P00 as a INT0, set bit 3 (SM3) of the shift mode register to 1. The serial interface function to use P01 to P03 as a serial interface I/O port is determined by bits 2 and 1 (SM2 and SM1) of the shift mode register. See 2.12 "SERIAL INTERFACE" for details. Even though this port operates using any function other than the port function, execution of the port input instruction (IPL) permits loading data on the P00 to P03 line to the accumulator (A0 to A3) at any time. (2) P80 to P83 (Port 8) The port 8 is a 4-bit output port with an output latch, which consists of 4-bit output pin. The port output instruction (OPL) latches the content of the accumulator (A0 to A3) to the output latch and outputs it to pins P80 to P83. The SPBL and RPBL instructionsNote allow bit-by-bit setting and resetting of pins P80 to P83. Note that P83 is to be selected using a mask option, to serve as one of the connection pins of the resistor R for RC oscillation (CL2) or as the bit 3 output of the port 8. Thus, the port 8 is a 3-bit output port (P80 to p82) if RC oscillation is performed, and provides a 4-bit output (P80 to P83) only when an external clock is used. For these ports, mask options for the output format are available to select CMOS (push-pull) output or N-ch opendrain output. The port specified as a N-ch open-drain output and provides an efficient interface to the circuit operating at a different supply voltage because the output buffer has a dielectric strength of 9 V. Contents of the output latch become undefined when the RESET signal is input, then the output becomes high impedance. Note RPBL and SPBL are bit-by-bit setting and resetting instructions. During setting and resetting operations, the RPBL and SPBL instructionrs allow outputting with each (4-bit) port which contains the specified bits. (The content of the output latch is output to any pin other than the specified pins.) The content of the output latch must be initialized with the OPL instruction before executing the RPBL and SPBL instructions.
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PD7554A, 7554A(A)
(3) P100 to P103 (Port 10) and P110-P113 (Port 11): Quasi-bidirectional input/output P100 to P103 are 4-bit I/O pins which form the port 10 (4-bit I/O port with an output latch). P110 to P113 are 4bit I/O pins which form the port 11 (4-bit I/O port with an output latch). The port output instruction (OPL) latches the content of the accumulator to the output latch and outputs it to the 4-bit pins. The data written once in the output latch and the output buffer state are retained until the output instruction to operate the port 10 or 11 is executed or the RESET signal is input. Even though an input instruction is executed for the port 10 or 11, the states of both the output latch and output buffer do not change. The SPBL and RPBL instructions allow bit-by-bit setting and resetting of pins P100 to P103 and P110 to P113. The input/output format of each of the ports 10 and 11 can be selected from among the N-ch open-drain input/ output, N-ch open-drain + pull-up resistor built-in input/output, and CMOS (push-pull) input/output by their respective mask options. The ports 10 and 11 offers the middle withstand voltage of 9 V for the N-ch open-drain input/output, so that they are convenient for interface between circuits which has different supply voltages. When the CMOS (push-pull) input/output is selected, the port cannot return to the input mode once the output instruction is executed. However, the states of the pins of the port can be checked by reading via the port input instruction (IPL). When one of the other two formats is selected, the port can enter the input mode to load the data on the 4-bit line to the accumulator (as a quasi-bidirectional port) when the port receives high level output. Select each type of the input/output format to meet the use of the port: CMOS input/output i) Uses all 4 bits of the port as input ports. ii) Uses pins of the port as output pins not requiring middle withstand voltage output. N-ch open-drain input/output i) Uses pins of the port as I/O pins requiring a middle withstand voltage dielectric strength. ii) Uses input pins of the port which also has output pins. iii) Uses each pin of the port for both input and output by switching them over. N-ch open-drain + pull-up resistor built-in input/output i) Uses input pins of the port which also has output pins, that require a pull-up resistor. ii) Uses each pin of the port for both input and output by switching them over. This requires a pull-up resistor. Caution Before using input pins in the case of or , write 1 in the output latch to turn the N-ch transistor off. The content of the output latch becomes undefined when the RESET signal is input. In such a case, the output becomes high level with the N-ch open-drain + pull-up resistor built-in, and becomes high impedance without the resistor.
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PD7554A, 7554A(A)
2. INTERNAL BLOCK FUNCTIONS
2.1 PROGRAM COUNTER (PC): 10 BITS
The program counter is a 10-bit binaryc ounter to retain program memory (ROM) address information. Fig. 2-1 Program Counter Configuration
PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PC
When one instruction is executed, usually the program counter is incremented by the number of bytes of the instruction. When the call instruction is executed, the PC is loaded with a nkew call address after the stack memory saves the current contents (return address) of the PC. When the return instruction is executed, the content (return address) of the stack memory is loaded onto the PC. When the jump instruction is executed, the immediate data identifying the destination of the jump is loaded to all or some of bits of the PC. When a skip occurs, the PC is incremented by 2 or 3 during the machine cycle depending on the number of bytes in the next instruction. When the RESET signal is input, all the bits of the PC are cleared to zero.
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PD7554A, 7554A(A)
2.2 STACK POINTER (SP): 6 BITS The stack pointer is a 6-bit register which retains head address information of the stack memory (LIFO type) which is a part of the data memory. Fig. 2-2 Stack Pointer Configuration
SP5 SP4 SP3 SP2 SP1 SP0 SP
The stack pointer is decremented when the call instruction is executed. It is incremented when the return instruction is executed. To determine the stack area, initialize the SP using the TAMSP instruction. Note that bit SP0 is loaded with 0 unconditionally when the TAMSP instruction is executed. Set the SP to the value of "the highest address of the stack area + 1" because the stack operation starts with decrementation of the SP. When the highest address of the stack area is 3FH which is the highest address of the data memory, the initial value of SP5-0 must be 00H. For emulation using the PD7500H (EVAKIT-7500B), set the data to be used for AM when executing the TAMSP instruction. Fig. 2-3 In Execution of TAMSP Instruction
A3
A2
A1
A0
(HL)3
(HL)2
(HL)1
(HL)0 0
SP5
SP4
SP3
SP2
SP1
SP0
Note that the contents of the SP cannot be read. Caution Be sure to set the SP at the initial stage of the program execution because the SP becomes undefined when the RESET signal is input. Example LHLI LAI ST LAI TAMSP 00H 0 4 ;SP = 40H
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PD7554A, 7554A(A)
2.3 PROGRAM MEMORY (ROM): 1024 WORDS x 8BITS The program memory is a mask programmable ROM of 1024 word x 8 bits configuration. It is addressed by the program counter. The program memory stores programs. Address 000H is the reset start address. Fig. 2-4 Program Memory Map
(0) 000H
Reset Start
(1023) 3FFH
2.4
GENERAL REGISTER
General registers H (with two bits) and L (with four bits) operate individually. They also form a pair register HL (H: high order and L: low order) to serve as a data pointer for addressing the data memory. Fig. 2-5 General Register Configuration
1 H 0 3 L 0
The L register is also used to specify I/O ports and the mode register when an input/output instruction (IPL or OPL) is executed. It also used to specify the bits of a port when the SPBL or RPBL instruction is executed.
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PD7554A, 7554A(A)
2.5 DATA MEMORY (RAM): 64 x 4 BITS The data memory is a static RAM of 64 word x 4 bits configuration. It is used as the area to store or stack processed data. The data memory may be processed in 8-bit units when paired with the accumulator. Fig. 2-6 Data Memory Map
( 0 ) 00H
64 Words x 4 Bits
(63) 3FH
The data memory is addressed in the following three ways: * Direct: Direct addressing based on immediate data of an instruction * Register indirect: Indirect addressing according to the contents of the pair register HL (including automatic incrementation and decrementation) * Stack: Indirect addressing according to the contents of the stack pointer (SP) An arbitrary space of the data memory is available as stack memory. The boundary of the stack area is specified when the TAMSP instruction initializes the SP. After that, the stack area is accessed automatically by the call or return instruction. After the call instruction is executed, the content of the PC and PSW is stored in the order shown in the following diagram:
Stack Area 3 SP - 4 SP - 3 SP - 2 SP - 1 0 0 PC9 0 PC8
PSWNote PC3 - PC0 PC7 - PC4 Note Bit 1 is fixed at 0.
When the return instruction is executed, the content of the PSW is not restored while those of the PC are restored. Data in the data memory is retained at a low supply voltage in the STOP mode.
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PD7554A, 7554A(A)
2.6 ACCUMULATOR (A): 4 BITS The accumulator is a 4-bit register which plays a major role in many types of arithmetic operations. The accumulator may be processed in 8-bit units when paired with the data memory addressed by the pair register HL. Fig. 2-7 Accumulator Configuration
A3
A2
A1
A0
A
2.7 ARITHMETIC LOGIC UNIT (ALU): 4 BITS The arithmetic logic unit is a 4-bit arithmetic circuit to perform arithmetic and bit processing such as binary addition, logical operation, incrementation, decrementation, and comparison. 2.8 PROGRAM STATUS WORD (PSW): 4 BITS The program status word consists of skip flags (SK1 and SK0) and a carry flag (C). Bit 1 of the PSW is fixed at 0. Fig. 2-8 Program Status Word Configuration
3 SK1 2 SK0 1 0 0 C PSW
(1) Skip flags (SK1 and SK0) Skip flags store the following skip status: * Stacking by the LAI instruction * Stacking by the LHLI instruction * Skip condition establishment by any instruction other than stack instructions The skip flags are set and reset automatically when respective instructions are executed. (2) Carry flag (C) The carry flag is set to 1 when a carry from bit 3 of the ALU occurs when the add instruction (ACSC) is executed. The flag is reset to 0 when the carry does not occur. The SC and RC instructions respectively set and reset the carry flag. The SKC instruction tests the contents of the flag. The content of the PSW are automatically stored in the stack area when the call instruction is executed. It cannot be restored by the return inhstruction. When the RESET signal is input, SK1 and SK0 are both cleared to zero and C becomes undefined.
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PD7554A, 7554A(A)
2.9 SYSTEM CLOCK GENERATOR The system clock generator contains an RC oscillator, 1/2 divider, and standby (STOP/HALT) mode control circuit. Fig. 2-9 System Clock Generator
STOP F/F Q S R HALT F/F Q S R R CL1 C 1/2 RC Oscillator HALTNote RESET (High) STANDBY RELEASE RESET ( ) STOP
Note
Oscillator Stop CL2
(To CPU)
CL (System Clock)
Note Instruction execution
The RC oscillator oscillates with an external resistor R connected to pins CL1 and CL2. (A capacitor C is incorporated.) The RC oscillator serves merely as a reverse buffer if inputs an external clock through the CL1 input. The RC oscillator outputs the system clock (CL) which is 1/2 divided to the CPU clock (). The control circuit in the standby mode consists mainly of STOP F/F and HALT F/F. The STOP F/F is set by the STOP instruction, blocking any clock from being supplied. The STOP F/F stops RC oscillation during operation of the RC oscillator (STOP mode). The STOP F/F is reset by the STANDBY RELEASE signal (which goes active when even one test request flag is input) or at the fall of the RESET input, to cause the RC oscillator to start oscillation and supplying each clock. The HALT F/F is set by the HALT instruction to disable the input to the 1/2 divider which generates the CPU clock
, stopping only the CPU clock (HALT mode). The HALT F/F is set and reset as in the case of the STOP F/F. Resetting the HALT F/F cause the RC oscillator to start supplying the CPU clock .
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PD7554A, 7554A(A)
2.10 CLOCK CONTROL CIRCUIT The clock control circuit consists of 2-bit clock mode registers (CM2 and CM1), prescalers 1, 2 and 3, and a multiplexer. The circuit inputs the system clock generator output (CL) and the event pulse (P00). It also selects a clock source and a prescaler according to the specifications of clock mode register and supplies a count pulse (CP) to the timer/event counter. Fig. 2-10 Clock Control Circuit
Internal Bus OPL CM2 CM1
Note
CL
PRESCALER 1 (1/4)
PRESCALER 2 (1/8)
PRESCALER 3 (1/8)
P00 CP
Note Instruction execution
Use the OPL instruction to set codes in the clock mode registers. Fig. 2-11 Clock Mode Register Format
CM2 CM1
Clock Mode Register
CM2 0 0 1 1
CM1 0 1 0 1
Count Pulse Frequency (CP) CL x P00 CL x CL x
1 32 1 4 1 256
Caution When setting codes in the clock mode registers using the OPL instruction, be sure to set bit 0 of the accumulator to 0. (Bit 0 corresponds to CM0 of the PD7500 of EVAKIT-7500B in emulation.)
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PD7554A, 7554A(A)
2.11 TIMER/EVENT COUNTER The timer/event counter is based on an 8-bit count register as shown in Fig. 2-12. Fig. 2-12 Timer/Event Counter
Internal Bus
TCNTAMNote
8
CP
Count Holding Circuit
8-BIT COUNT REG CLR TIMERNote RESET
INTT (To Test Control Circuit)
Note Instruction execution
The 8-bit count register is a binary 8-bit up-counter which is incremented whenever a count pulse (CP) is input. The register is cleared to 00H when the TIMER instruction is executed, RESET signal is input, or an overflow occurs (FFH to 00H). As the count pulse, the clock mode register can select one of the following four. See 2.10 "CLOCK CONTROL CIRCUIT".
1 1 1 CP : CL x --, CL x ---, CL x ----, P00 4 32 256
The count register continues to be incremented as long as count pulses are input. The TIMER instruction clears the count register to 00H and triggers the timer operation. The count register is incremented in synchronization with the CP (or the rise of the P00 input when an external clock is used). On the count reaches 256, the register returns the count value to 00H from FFH, generates the overflow signal INTT, and sets the INTT test flag INTT RQF. In this way, the count register counts over from 00H. To recognize the overflow, test the flag INTT RQF using the SKI instruction. When the timer/event counter serves as a timer, the reference tiome is determined by the CP frequency. The precision is determined by the RC oscillation or CL1 external input frequency when the system clock system is selected and by the P00 input frequency when the P00 input is selected. The content of the count register can be read at any time by the TCNTAM instruction. This function allows checking the current time of the timer and counting event pulses input to the P00 input. This enables the number of even pulses that have been generated so far (event counter function). The count holding circuit ignores the change of the count pulse (CP) during execution of the TCNTAM instruction. This is to prevent reading undefined data in the count register using the TCNTAM instruction while the counter is being updated. Since the timer/event counter operates the system clock system (CL) or the P00 input for count pulses, it is used to cancel the HALT mode which stops the CPU clock as well as the STOP mode which stops the system clock CL. (See 3 "STANDBY FUNCTIONS".)
22
PD7554A, 7554A(A)
2.12 SERIAL INTERFACE The serial interface consists of an 8-bit shift register, 3-bit shift mode register, and 3-bit counter. It is used for input/output of serial data. Fig. 2-13 Serial Interface Block Diagram
Internal Bus IPL P03/SI LSB
Note
4
TSIOAMNote
8
8
TAMSIONote
OPLNote SHIFT MODE REG
8-BIT SHIFT REG
MSB
P02/SO 3-BIT CNT
SM3
P01/SCK
P00/INT0
INT0
R RS F/F Q S
INTS SIO
Note
Note Instruction execution Remarks 1. indicates the internal clock signal (system clock). 2. SM3 and INT0 go to the test control circuit. Input/output of serial data is controlled by the serial clock. The highest bit (bit 7) of the shift register is output from the SO line at rise of the serial clock (SCK pin signal). At its fall, the contents of the shift register is shifted by one bit (bit n -> bit n+1) and data on the SI line is loaded to the lowest bit (bit 0) of the shift register. The 3-bit counter (octal counter) counts serial clock pulses. Wthenever it counts eight clock pulses (on completion of 1-byte serial data transfer), the counter generates an internal test request signal INTS to set the test request flag (INT0/S RQF). Fig. 2-14 Shift Timing
SCK SI SO DI7 MSB DO7 DO6 DO5 DO4 DO3 DO2 DO1 DI6 DI5 DI4 DI3 DI2 DI1 DI0 LSB DO0 INTS RQF Setting Timing
Remarks
1. DI: Serial data input 2. DO: Serial data output
23
PD7554A, 7554A(A)
The serial interface sets serial data for transmission in the shift register using the TAMSIO instruction and starts the transfer using the SIO instruction. To recognize the termination of one-byte transfer, check the test request flag INT0/S RQF using the corresponding instruction. The serial interface starts serial data reception, using the SIO instruction, checks the termination of one-byte transfer using the instruction, and then receives data from the shift register by executing the TSIOAM instruction. Two types of serial clock sources are available: one is the system clock and the other is the external clock (SCK input). They are selected respectively by bits 2 and 1 (SM2 and SM1) of the shift mode register. When the system clock is selected and the SIO instruction is executed, the clock pulse is supplied to the serial interface as a serial clock to control serial data input/output and is output from the SCK pin. When the system clock pulse is supplied eight times, the supply to the serial interface is automatically stopped and the SCK output remains high. Since serial data input/output stops automatically after transfer of one byte. The programmer does not need to control the serial clock. In this case, the transfer speed is determined by the system clock frequency. In this mode, it is possible to read receive data (by the TSIOAM instruction) and write data (by the TAMSIO instruction) from and to the shift register only by waiting for 6 machine cycles after execution of the SIO instrucction on the program without waiting until the INT0/S RQF is set. Fig. 2-15 TAMSIO/TSIOAM Instruction Execution Timing
Instruction Execution Machine Cycle
SIO
Wait (6 Machine Cycle)
TAMSIO TSIOAM
SCK
When the external clock (SCK input) is selected, the interface inputs serial clock pulses from the SCK input. When an external serial clock pulse is input eight times, the INT0/S RQF is set and the termination of one-byte transfer can be recognized. However, the eight serial clocks to be input must be counted on the side of the external clock source because serial clock disable control is not performed internally. The transfer speed is determined by the external serial clock within the range from DC to the maximum value limited by the standard. When the external clock is used, the SIO, TAMSIO, or TSIOAM instruction the execution must be executed while the serial clock pulse SCK is high. If such an instruction is executed while the SCK is rising or falling or is low, the function of the instruction is not guaranteed.
24
PD7554A, 7554A(A)
Fig. 2-16 Shift Mode Register Format
SM3
SM2
SM1
Shift Mode Register
Settings for serial interface operation and the associated mode of the port 0
SM2 0 0 1 1 SM1 0 1 0 1 SI input SO output P03/SI Port input P02/SO Port input P01/SCK Port input Serial Operation Stop Operation based on external clock Operation based on
continuous output
SCK input SCK output ( x 8)
INT0/INTS selection
SM3 Test Sources
0 1
INTS INT0
Caution When setting a code in the shift mode register using the OPL instruction, be sure to set bit 0 of the accumulator to 0 (Bit 0 corresponds to CM0 of the PD7500H of EVAKIT-7500B in emulation). In the system which does not require serial interface, the 8-bit shift register can be used as a simple register and data can be read or writtene by the TSIOAM or TAMSIO instruction when serial operation is off. 2.13 TEST CONTROL CIRCUIT The PD7554A is provided with the following three types of test sources (one external source and two internal sources):
Test Sources INTT (Overflow from timer/event counter) INT0 (Test request signal from P00 pin) INTS (Transfer end signal from serial interface) Internal/External Internal External Internal Request Flag INTT RQF INT 0/S RQF
The test control circuit checks consist mainly of test request flags (INTT RQF and INT0/S RQF) which are set by three different test sources and the test request flag control circuit which checks the content of test request flags using the SKI instruction and controls resetting the checked flags. The INT0 and INTS are common in the request flag. Which one is selected is determined by bit 3 (SM3) of the shift mode register.
SM3
Test Sources
0 1
INTS INT0
25
PD7554A, 7554A(A)
The INTT RQF is set when a timer overflow occurs and is reset by the SKI or TIMER instruction. The INT0/S request flag functions in the following two ways according to the setting of the SM3: (1) SM3 = 0 The INTS is validated. The request flag INT0/S RQF is set when the INTS signal to indicate the termination of 8bit serial data transfer is issued. The flag is reset when the SKI or SIO instruction is executed. (2) SM3 = 1 The IN0 is validated. The request flag INT0/S RQF is set when the leading edge signal enters the INT0/P00 pin. The flag is reset when the SKI instruction is executed. The OR output of each test request flag is used to cancel the standby mode (STOP/HALT mode). If one or more request flags are set in the standby mode, the standby mode is cancelled. The RESET signal cancels every request flag and the SM3. In the reset initial status, the INTS is selected and the INT0 input is disabled. Fig. 2-17 Test Control Circuit Block Diagram
Internal Bus OPL SM3
Note
SKINote TEST RQF CONTROL
INTT
NONSYNC EDGE GATE TIMERNote
S R
INTT RQF
Q
INTS INT0
NONSYNC EDGE GATE
S INT0/S Q R RQF
STANDBY RELEASE
SIONote
Note Instruction execution Remark SM3 is bit 3 of the shift mode register.
26
PD7554A, 7554A(A)
3. STANDBY FUNCTIONS
The PD7554A provides two types of standby modes (STOP and HALT modes) to save power while the program is on standby. The STOP and HALT modes are set by the STOP and HALT instructions, respectively. The standby mode halts program execution, however, it holds the contents of all the internal registers and data memory that have been stored. The timer can operate even in the standby mode. The standby mode is canceled when the test request flag (INTT RQF or INT0/S RQF) is set or by RESET input. Note that if even one test request flag is set, the device cannot enter either the STOP or HALT mode even though the STOP or HALT instruction is executed. Before setting the standby mode at a point where a test request flag may be set, execute the SKI instruction to reset the test request flag. Table 3-1 relates the STOP mode to the HALT mode. An essential difference between them is found when RC oscillation supplies the system clock: by stopping the oscillation, the CL output stops in the STOP mode and does not stop in the HALT mode. Thus the amount of the power consumption of the RC oscillator equals to the difference in the amounts of the basic power consumption between the STOP mode and HALT mode. Note that the STOP mode enables the low supply voltage data to be retained in the data memory. Table 3-1 The Relation Between STOP and HALT Modes
Setting Instruction STOP mode HALT mode STOP HALT RC Oscillation (CL) x x q q x q
P00
CPU
Timer v
Cancellation Factor INTT RQF INT0/S RQF RESET input
q : Operation enabled v : Operation enabled depending on mode selection x : Stop
3.1 STOP MODE The STOP mode stops the RC oscillation and 1/2 divider in the system clock generator. Therefore, the operations of requiring the system clock stubsystem (CL and ) such as the CPU are stopped. Since the STOP mode allows operation of the clock control circuit, the timer can operate if the P00 input is selected as the count pulse (CP). Note that the STOP mode stops only the signal, allowing the CL output when system clock generation is not drived by the RC oscillation, but drived by the external CL1 input. In such a case, the STOP mode causes the same state as in the case of the HALT mode described below. Therefore, the STOP instruction is effective for setting the STOP mode only during RC oscillation. 3.2 HALT MODE
The HALT mode stops only the 1/2 divider in the system clock generator (allowing operation of the system clock CL and stopping the CPU clock ). Therefore, the operations of the CPU requiring the signal is stopped in the HALT mode. Since the HALT mode allows operation of the clock control circuit, the circuit inputs the CL signal from the clock generator and the external count clock (P00) to supply the count pulses (CP) for both subsystems selectively to the timer. Thus, the timer can operate depending on the both-system count pulses and continue counting time.
27
PD7554A, 7554A(A)
3.3
CANCELLING THE STANDBY MODE
(1) Cancelling the STANDBY mode by test request flag As well as the STOP mode and HALT mode, the STANDBY mode is canceled when the test request flag (INTT RQF or INT0/S RQF) is set in the mode. The program starts executing the instruction that follows the HALT instruction that follows the STOP or HALT instruction. Cancellation of the HALT mode does not affect the content of any register or the data memory, that is retained in the mode. (2) Cancelling the STANDBY mode by RESET input RESET input unconditionally cancels the STANDBY mode as well as nthe STOP mode and HALT mode. Fig. 3-1 shows the STANDBY mode cancel timing. Fig. 3-1 STANDBY Mode Cancel Timing by RESET Input
RESET
Operating Mode
STOP/HALT Mode Cancellation Normal Reset Operation (Starting from address 0) STOP/HALT Instruction
The STANDBY mode is maintained while the RESET input is being active (high). When the RESET input goes low, the STANDBY mode is cancelled and the CPU starts to execute the program from address 0 after a normal reset operation. Note that RESET input does not affect the content of the data memory that is retained in the STANDBY mode, however, the contents of the other registers become undefined on cancellation of the mode.
28
PD7554A, 7554A(A)
4. RESET FUNCTIONS
The PD7554A is reset and initialized when the RESET pin inputs a high or active RESET signal as follows: 4.1 DETAILS OF INITIALIZATION
(1) The program counter (PC9-PC0) is cleared to zero. (2) The skip flags (SK1 and SK0) in the program status word are reset to zero. (3) The count register in the timer-event counter is cleared to 00H. (4) The clock control circuit becomes as follows: * Clock mode registers (CM2 and CM1) = 0
1 (c) CP = CL x ----- 256 * Prescalers 1, 2, and 3 = 0 (5) The shift mode register (SM3 to SM1) is cleared to zero. Shifting of the serial interface is stopped. The port 0 enters the input mode (high impedance).
Note1
INT0/S, INTS is selected. (6) The test request flag (INTT RQF or INT0/S RQF) is reset to zero. (7) The contents of the data memory and the following registers become undefined: Stack pointer (SP) Accumulator (A) Carry flag (C) General registers (H and L) Output latch of each port (8) The output buffer of every port goes off and has high impedance
Note2.
The I/O port enters the input mode.
Note 1. When the pull-up and pull-down resistors are selected using a mask option, the former has high level and the latter has low level. 2. When the pull-up and pull-down resistors are selected in the port 0 using a mask option, the former has high level and the latter has low level. When the pull-up resistor is selected in the ports 10 and 11 using a mask option, the resistor has high level. Caution When the STANDBY mode is cancelled by the RESET signal, the content of the data memory is retained without becoming undefined. When the RESET input is cancelled, the program is executed starting with address 000H. The content of each register shall either be initialized in the process of the program or reinitialized depending on conditions.
29
PD7554A, 7554A(A)
5. PD7554A INSTRUCTION SET
(1) Operand representation and description
addr caddr caddr1 mem n5 n4 n2 bit pr 10-bit immediate data or label 10-bit immediate data or label 100H to 107H, 140H to 147H, 180H to 187H, IC0H to IC7H immediate data or label 6-bit immediate data or label 5-bit immediate data or label 4-bit immediate data or label 2-bit immediate data or label 2-bit immediate data or label HL-, HL+, HL
(2) Mnemonics for operation descriptions A : Accumulator H L HL pr SP PC C PSW SIO CT In Pn Bn Dn Rn (xx) xH : H register : L register : Pair register HL : Pair register HL-, HL+, or HL : Stack pointer : Program counter : Carry flag : Program status word : Shift register : Count register : Immediate data to n5, n4 or n2 : Immediate data to addr, caddr, or caddr1 : Immediate data to bit : Immediate data to mem : Immediate data to pr : Content addressed by xx : Hexadecimal data
30
PD7554A, 7554A(A)
(3) Port/mode register selection
IPL Instruction
L 0 AH BH Port Port 0 Port 10 Port 11
OPL Instruction
L 8 AH BH CH FH Port/mode register Port 8 Port 10 Port 11 Clock mode register Shift mode register
RPBL/SPBL Instruction
L Bit Port FH 3 EH 2 Port 11 DH 1 CH 0 BH 3 AH 2 9 1 Port 10 8 0 3 3 2 2 Port 8 1 1 0 0
(4) Selection of pair register addressing
pr HL- HL+ HL R1 0 0 1 R0 0 1 0
31
Note
Mnemonic LAI LHI
Operands n4 n2 pr n5 0 0 0 1 0 n4 0 0 pr n4 0 0 0 0 0 1 1 1 1 1 1 0 1 0 1 0 0 0 0 1 0 0 1
Operation Code B1 1 0 1 I4 1 0 1 1 0 1 I3 1 0 I3 0 I3 1 0 I3 1 I2 0 I1 I1 I0 I0 B2 An4 Hn2 A(pr) pr = HL -, HL +, HL H0I4, LI3-0 (HL)A (HL)n4, LL+1 AL A(pr) pr = HL - , HL + , HL AA + n4 AA + (HL)
Operation Loads n4 to the accumulator. Loads n2 to H register. Loads the contents of the memory address by pr to the accumulator. Loads n5 to the pair register HL. Stores the contents of the accumulator in the memory addressed by HL. Stores n4 in the memory addressed by HL and increments the L register. Exchanges the contents of the accumulator and the L register. Exchanges the contents of the accumulator and the memory addressed by pr. Adds the accumulator to n4. Adds the contents of the accumulator and the memory addressed by HL. Adds the contents of the accumulator, the memory addressed by HL, and of the carry flag. Calculate the exclusive OR of the contents of the accumulator and the memory addressed by HL. Complements the accumulator. Resets the carry flag. Sets the carry flag. Increments the L register. Increments the contents of the memory addressed by mem. Decrements the L register. Decrements the contents of the memory addressed by mem. Resets the bits specified by B1-0, of the memory addressed by HL.
Skip Condition Stack LAI
Load/Store Instructions
Operation Instructions
Accumulator & Carry Flag Manipulation Instructions
Increment/Decrement Instructions
Memory Bit Manipulation Instructions
32
LAM LHLI ST STII XAL XAM AISC ASC
0 R1 R0 I2 1 I2 0 I1 1 I1 1 I0 1 I0 1
L = FH(HL -) L = 0 (HL +) Stack LHLI
1 R1 R0 I2 1 I1 0 I0 1
L = FH(HL-) L = 0 (HL+) Carry Carry
ACSC
0
1
1
1
1
1
0
0
A, CA + (HL) + C
Carry
EXL CMA RC SC ILS IDRS DLS DDRS RMB mem bit mem
0 0 0 0 0 0 0 0 0
1 1 1 1 1 0 1 0 1
1 1 1 1 0 1 0 1 1
1 1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1 1
1 1 0 0 0 1 0 1
1 1 0 0 0 0 0 0
0 1 0 1 1 1 0 0 0 0 D5 D4 D3 D2 D1 D0 0 0 D5 D4 D3 D2 D1 D0
AA (HL) -- AA C0 C1 LL + 1 (mem)(mem) + 1 LL - 1 (mem)(mem) - 1 (HL)bit0
L=0 (mem) = 0 L = FH (mem) = FH
PD7554A, 7554A(A)
0 B1 B0
SMB
bit
0
1
1
0
1
1 B1 B0
(HL)bit1
Sets the bits specified by B1-0, of the memory addressed by HL.
Note
Instruction Group
Note
Jump Instructions
Mnemonic JMP JCP
Operands addr addr 0 1 0 0 1
Operation Code B1 0 0 0 B2 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 PC9-0P9-0 PC5-0P5-0 (SP-1)(SP-2)(SP-4)PC9-0 (SP-3)PSW, SPSP - 4 PC9-0P9-0
Operation Jumps to the address specified by P9-0. Jumps to the address specified by replacing PC5-0 with P5-0. Saves the contents of PC and PSW to the stacxk memory, decrements SP by 4, and calls the address specified by caddr.
Skip Condition
P5 P4 P3 P2 P1 P0
Subroutine/stack control instructions
CALL
caddr
0
0
1
1
0
0
P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
CAL
caddr1 1
1
1
P4 P3 P2 P1 P0
(SP-1)(SP-2)(SP-4)PC9-0 Saves the contents of PC and PSW to the (SP-3)PSW, SPSP - 4 stacxk memory, decrements SP by 4, and PC9-00 1 P4 P3 0 0 0 P2 P1 P0 calls the address specified by caddr1. PC9-0(SP)(SP+2)(SP+3) SPSP + 4 PC9-0(SP)(SP+2)(SP+3) SPSP + 4 then skip unconditionally PC5-4A1-0 SP3-1(HL)3-1, SP00 Skip if C = 1 Skip if Abit = 1 Restores the contents of the stack memory to PC, and increments SP by 4. Restores the contents of the stack memory to PC, increments SP by 4, and causes unconditional skipping. Transfers the two low-order bits of the accumulator to SP5-4 and the three highorder bits of the memory addressed by HL to SP3-1. Causes skipping if the carry flag is 1. Causes skipping of the bit of the accumulator, which is specified by B1-0 is 1. Causes skipping of the bit of the memory addressed by HL, which is specified by B1-0 is 1. Causes skipping of the bit of the memory addressed by HL, which is specified by B1-0 is 0. Causes skipping if the contents are the same between the accumulator and the memory addressed by HL. Skips if the accumulator is equal to n4. Skips if INT RQF is 1, and then sets INT RQF to 0. C=1 Abit = 1 Unconditionally
RT
0
1
0
1
0
0
1
1
RTS
0
1
0
1
1
0
1
1
TAMSP
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
1
SKC SKABT bit
0 0
1 1
0 1
1 1
1 0
0
1
0
1 B1 B0
Skip Instructions
SKMBT bit
0
1
1
0
0
1 B1 B0
Skip if (HL)bit = 1
(HL)bit = 1
SKMBF
bit
0
1
1
0
0
0 B1 B0
Skip if (HL)bit = 0
(HL)bit = 0
PD7554A, 7554A(A)
SKAEM SKAEI SKI n4 n2
0 0 0
1 0 0
0 1 1
1 1 1
1 1 1
1 1 1
1 1 0
1 1 1 0 0 1 1 1 0 0 0 I3 0 I2 0 I1 I1 I0 I0
Skip if A = (HL) Skip if A = n4 Skip if INT RQF = 1 Then reset INT RQF
A = (HL) A = n4 INT RQF = 1
Note 33
Instruction Group
SIO control instructions
Timer control instructions
Input/output instructions
CPU control Instructions
34
Note1
Mnemonic
Operands
Operation Code B1 B2 SIO7-4A
Operation Transfers the contents of the accumulator
Skip Condition
TAMSIO
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
0
SIO3-0(HL)
to the four high-order bits of the shift register and the contents of the memory addressed by HL to the four low-order bits. Transfers the four high-order bits of the shift register to the accumulator and the four low-order bits to the memory addressed by HL. Starts shifting. Starts timer operation. Transfers the four high-order bits of the count register to the accumulator and the four low-order bits to the memory addressed by HL. Loads the contents of the port specified by the L register to the accumulator.
TSIOAM
0
0
1
1
1
1
1
1
0
0
1
1
1
0
1
0
ASIO7-4 (HL)SIO3-0 Start SIO Start Timer ACT7-4
SIO TIMER
0 0
0 0
1 1
1 1
1 1
1 1
1 1
1 1
0 0
0 0
1 1
1 1
0 0
0 0
1 1
1 0
TCNTAM
0
0
1
1
1
1
1
1
0
0
1
1
1
0
1
1
(HL)CT3-0
IPL
0
1
1
1
0
0
0
0
APort (L)
OPL
Note2
0
1
1
1
0
0
1
0
RPBL SPBL
0 0 0 0 0
1 1 0 0 0
0 0 1 1 0
1 1 1 1 0
1 1 1 1 0
1 1 1 1 0
0 0 1 1 0
0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 1
Outputs the contents of the accumuPort/Mode reg. (L)A lator to the port specified by the L register or the mode register. Resets the bits of ports 8, 10, and 11, Port bit (L)0 that are specified by the L register. Port bit (L)1 Set Halt Mode Set Stop Mode No operation Sets the bits of ports 8, 10, and 11, that are specified by the L register. Sets the HALT mode. Sets the STOP mode. Performs no operation for one machine cycle.
Note2
HALT STOP NOP
PD7554A, 7554A(A)
Note 1. Instruction Group 2. SPBL and RPBL are bit-wise set/reset instructions. They perform output to each 4-bit port including the specified bits as well as set and reset operation (They output the contents of the output latch to bits other than the specified bits.). Before executing these instructions, intialize the contents of the output latch using the OPL instruction.
PD7554A, 7554A(A)
6. ELECTRICAL SPECIFICATIONS
PD7554A: ABSOLUTE MAXIMUM RATINGS (Ta = 25 C)
Parameter Supply voltage Symbol VDD Except ports 10 and 11 Input voltage VI Ports 10 and 11 Except ports 8, 10, 11 Output voltage VO Ports 8, 10 and 11 1 pin All pins in total P01, P02 Output current low IOL 1 pin Port 8 Others All pins in total Operating temperature Storage temperature Power consumption Topt Tstg Pd Ta = 70 C Shrink DIP Mini flat Note 1 Note 2 Output current high IOH Note 1 Note 2 Test Conditions Rating -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +11 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +11 -5 -15 5 30 15 100 -10 to +70 -65 to +150 480 250 Unit V V V V V V V mA mA mA mA mA mA C C mW
Note 1. 2.
CMOS input/output or N-ch open-drain output + pull-up resistor built-in input/output N-ch open-drain input/output
Caution Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. Be sure not to exceed or fall below this value when using the product.
5
35
PD7554A, 7554A(A)
PD7554A(A): ABSOLUTE MAXIMUM RATINGS (Ta = 25 C)
Parameter Supply voltage Symbol VDD Except ports 10 and 11 Input voltage VI Ports 10 and 11 Except ports 8, 10, 11 Output voltage VO Ports 8, 10 and 11 1 pin All pins in total P01, P02 Output current low IOL 1 pin Port 8 Others All pins in total Operating temperature Storage temperature Power consumption Topt Tstg Pd Ta = 85 C Shrink DIP Mini flat Note 1 Note 2 Output current high IOH Note 1 Note 2 Test Conditions Rating -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +11 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +11 -5 -15 5 30 15 100 -40 to +85 -65 to +150 350 195 Unit V V V V V V V mA mA mA mA mA mA C C mW
Note 1. 2.
CMOS input/output or N-ch open-drain output + pull-up resistor built-in input/output N-ch open-drain input/output
Caution Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. Be sure not to exceed or fall below this value when using the product. CAPACITY (Ta = 25 C, VDD = 0 V)
Parameter Input capacity Output capacity I/O capacity Symbol CIN COUT CIO f = 1 MHz Unmeasured pins returned to 0 V. Test Conditions P00, P03 Port 8 P01, P02 Ports 10 and 11 MIN. TYP. MAX. 15 35 15 35 Unit pF pF pF pF
36
PD7554A, 7554A(A)
RESONATOR CHARACTERISTICS
PD7554A : Ta = -10 to +70 C, VDD = 2.7 to 6.0 V PD7554A(A) : Ta = -40 to +85 C, VDD = 2.7 to 6.0 V
Test Conditions VDD = 5 V 10% R = 56 k 2 % VDD = 3 V 10% R = 100 k 2% Duty = 50% VDD = 4.5 to 6.0 V MIN. 400 200 10 10 TYP. 500 250 MAX. 600 300 710 350 0.2 VDD = 4.5 to 6.0 V 0.7 1.45 50 50 Unit kHz kHz kHz kHz
Parameter System clock oscillator frequency (CL1 and CL2) System clock input frequency (CL1) CL1 input rising and falling time CL1 input high/low level duration
Symbol
fCC
fC
tCR, tCF tCH, tCL
s s s
RESONATOR CHARACTERISTICS (Ta = -10 to +70 C, VDD = 2.5 to 3.3 V)Note
Parameter System clock oscillator frequency (CL1 and CL2) System clock input frequency (CL1) CL1 input rising and falling time CL1 input high/low level duration Symbol fCC Test Conditions R = 150 k 2% R = 150 k 2% VDD = 2.5 V Duty = 50 % MIN. 140 140 10 TYP. 180 175 MAX. 220 210 250 0.2 2 50 Unit kHz kHz kHz
fC tCR, tCF tCH, tCL
s s
RESONATOR CHARACTERISTICS (Ta = -10 to +70 C, VDD = 2.0 to 3.3 V)Note
Parameter System clock oscillator frequency (CL1 and CL2) System clock input frequency (CL1) CL1 input rising and falling time CL1 input high/low level duration Symbol fCC Test Conditions R = 240 k 2% R = 240 k 2% VDD = 2.0 V Duty = 50 % MIN. 65 65 10 TYP. 120 100 MAX. 145 130 150 0.2 3.3 50 Unit kHz kHz kHz
fC tCR, tCF tCH, tCL
s s
Note PD7554A only The following circuits are recommended:
RC oscillation
PD7554A
External clock
PD7554A
CL1
CL2
CL1
CL2
Leave Open R CMOS
37
PD7554A, 7554A(A)
DC CHARACTERISTICS
PD7554A : Ta = -10 to +70 C, VDD = 2.7 to 6.0 V PD7554A(A) : Ta = -40 to +85 C, VDD = 2.7 to 6.0 V
Symbol VIH1 Except CL1 CL1 Ports 10 and 11 Except CL1 CL1 VDD = 4.5 to 6.0 V IOH = -1 mA IOH = -100 A P01, P02 VDD = 4.5 to 6.0 V IOL = 1.6 mA IOL = 400 A VDD = 4.5 to 6.0 V IOL = 1.6 mA
Note1
Parameter
Test Conditions
MIN. 0.7VDD VDD - 0.5 0.7VDD 0 0 VDD - 2.0 VDD - 1.0
TYP.
MAX. VDD VDD 9 0.3VDD 0.5
Unit V V V V V V V
Input voltage high
VIH2 VIH3
Input voltage low
VIL1 VIL2
Output voltage high
VOH
0.4 0.5 0.4 2.0 0.5 2.0 0.5 3 10
V V V V V V V
Output voltage low
VOL
Ports 10 and 11
VDD = 4.5 to 6.0 V IOL = 10 mA IOL = 400 A
Port 8
VDD = 4.5 to 6.0 V IOL = 15 mA IOL = 600 A
ILIH1 Input leak current high ILIH2 ILIH3 Input leak current low ILIL1 ILIL2 Output leak current high Output leak current low Input pin built-in resistor (pull-up/down resistor) Output pin built-in resistor (pull-up resistor) ILOH1 ILOH2 ILOL
VIN = VDD
Except CL1 CL1
A A A A A A A A
K K
VIN = 9 V, ports 10 and 11 VIN = 0 V VOUT = VDD
Note1
10 -3 -10 3
Note1
Except CL1 CL1
VOUT = 9 V, ports 8, 10, and 11 VOUT = 0 V Port 0, RESET Ports 10 and 11
10 -3 23.5 7.5 47 15 270 80 120 35 0.1 0.1 70.5 22.5 900 240 400 110 10 5
IDD1
Operating mode
VDD = 5 V 10 % R = 56 k 2 % VDD = 3 V 10 % R = 100 k 2 % VDD = 5 V 10 % R = 56 k 2 % VDD = 3 V 10 % R = 100 k 2 % VDD = 5 V 10 % VDD = 3 V 10 %
A A A A A A
Supply current
Note2
IDD2
HALT mode
IDD3
STOP mode
Note 1. For N-ch open-drain input/output selection 2. The current flowing in built-in pull-up and pull-down resistors is excluded.
38
PD7554A, 7554A(A)
AC CHARACTERISTICS
PD7554A : Ta = -10 to +70 C, VDD = 2.7 to 6.0 V PD7554A(A) : Ta = -40 to +85 C, VDD = 2.7 to 6.0 V
Symbol tCY Note Test Conditions VDD = 4.5 to 6.0 V MIN. 2.8 5.7 TYP. MAX. 200 200 710 350 0.2 VDD = 4.5 to 6.0 V 0.7 1.45 Input VDD = 4.5 to 6.0 V 2.0 2.5 5.0 5.7 VDD = 4.5 to 6.0 V 1.0 1.25 2.5 2.85 100 100 VDD = 4.5 to 6.0 V 850 1200 Unit
Parameter Internal clock cycle time
s s
kHz kHz
P00 event input frequency P00 input rise/fall time P00 input high/low level width
fPO tPOR, tPOF tPOH, tPOL
Duty = 50%
VDD = 4.5 to 6.0 V
0 0
s s s s s s s s s s s
ns ns ns ns
SCK cycle time
tKCY
Output Input Output Input
SCK high/low level width
tKH, tKL
Output Input Output
SI setup time (to SCK) SI hold time (from SCK) SCK SO output delay time INT0 high/low level width RESET high/low level width
tSIK tKSI tKSO tIOH, tIOL tRSH, tRSL
10 10
s s
Note tCY = 2/fCC or 2/fC AC Timing Test Point (Except CL1 Input)
0.7 VDD 0.3 VDD
Test Points
0.7 VDD 0.3 VDD
39
PD7554A, 7554A(A)
DC CHARACTERISTICS (Ta = -10 to +70 C, VDD = 2.5 to 3.3 V)Note1
Parameter Symbol VIH1 Input voltage high VIH2 VIH3 VIL1 Input voltage low VIL2 VIL3 Output voltage high VOH P01, P02 Output voltage low VOL Ports 10 and 11 Port 8 ILIH1 Input leak current high ILIH2 ILIH3 Input leak current low ILIL1 ILIL2 Output leak current high Output leak current low Input pin built-in resistor (pull-up/down resistor) Output pin built-in resistor (pull-up resistor) IDD1 Supply current Note3 ILOH1
ILOH2
Test Conditions Except CL1 CL1 Ports 10 and 11 Except CL1 CL1 Ports 10 and 11 IOH = -80 A IOL = 350 A IOL = 350 A IOL = 500 A Except CL1 CL1 VIN = 9 V, ports 10 and 11 VIN = 0 V VOUT = VDD VOUT = 9 V, ports 8, 10, and 11 VOUT = 0 V Port 0, RESET Ports 10 and 11 Operating mode VDD = 3 V 10% VDD = 2.5 V VDD = 3 V 10% VDD = 2.5 V
Note2 Note2 Note2
MIN. 0.8 VDD VDD - 0.3 0.8 VDD 0 0 0 VDD - 1.0
TYP.
MAX. VDD VDD 9 0.2VDD 0.3 0.2VDD
Unit V V V V V V V
0.5 0.5 0.5 3 10 10 -3 -10 3 10 -3 23.5 7.5 47 15 55 40 25 18 0.1 70.5 22.5 180 150 80 60 5
V V V
VIN = VDD
A A A A A A A A
K K
Except CL1 CL1
ILOL
A A A A A
IDD2 IDD3
R= 150 k HALT mode 2% STOP mode
Note 1. 2. 3.
PD7554A only For N-ch open-drain input/output selection The current flowing in built-in pull-up and pull-down resistors is excluded.
40
PD7554A, 7554A(A)
AC CHARACTERISTICS (Ta = -10 to +70 C, VDD = 2.5 to 3.3 V)Note1
Parameter Internal clock cycle time P00 event input frequency P00 input rise/fall time P00 input high/low level width SCK cycle time Symbol tCY
Note2
Test Conditions
MIN. 8.0 0
TYP.
MAX. 200 250 0.2
Unit
s
kHz
fPO tPOR, tPOF tPOH, tPOL Input Output
s s s s s s
ns ns
2.0 8.0 10.0 4.0 5.0 300 300 CL = 100 pF 30 30 2000
tKCY
SCK high/low level width SI setup time (to SCK) SI hold time (from SCK) SCKSO output delay time INT0 high/low level width RESET high/low level width
tKH, tKL tSIK tKSI tKSO tIOH, tIOL tRSH, tRSL
Input Output
ns
s s
Note 1. 2.
PD7554A only tCY = 2/fCC or 2/fC
AC Timing Test Point (Except CL1 Input)
0.8 VDD 0.2 VDD
Test Points
0.8 VDD 0.2 VDD
41
PD7554A, 7554A(A)
DC CHARACTERISTICS (Ta = -10 to +70 C, VDD = 2.0 to 3.3 V)Note1
Parameter Symbol VIH1 Input voltage high VIH2 VIH3 VIL1 Input voltage low VIL2 VIL3 Output voltage high VOH P01, P02 Output voltage low VOL Ports 10 and 11 Port 8 ILIH1 Input leak current high ILIH2 ILIH3 Input leak current low ILIL1 ILIL2 Output leak current high Output leak current low Input pin built-in resistor (pull-up/ down resistor) Output pin built-in resistor (pull-up resistor) IDD1 Supply current
Note3
Test Conditions Except CL1 CL1 Ports 10 and 11 Except CL1 CL1 Ports 10 and 11 IOH = -70 A IOL = 270 A IOL = 300 A IOL = 400 A Except CL1 CL1 VIN = 9 V, ports 10 and 11 VIN = 0 V VOUT = VDD VOUT = 9 V, ports 8, 10, and 11 VOUT = 0 V Port 0, RESET Ports 10 and 11 Operating mode VDD = 3 V 10% VDD = 2.0 V VDD = 3 V 10% VDD = 2.0 V
Note2 Note2 Note2
MIN. 0.85VDD VDD - 0.2 0.85VDD 0 0 0 VDD - 1.0
TYP.
MAX. VDD VDD 9 0.15VDD 0.2 0.2VDD
Unit V V V V V V V
0.5 0.5 0.5 3 10 10 -3 -10 3 10 -3 23.5 7.5 47 15 38 20 17 8 0.1 70.5 22.5 130 70 60 25 5
V V V
VIN = VDD
A A A A A A A A
K K
Except CL1 CL1
ILOH1 ILOH2 ILOL
A A A A A
IDD2 IDD3
R= 240 k HALT mode 2% STOP mode
Note 1. 2. 3.
PD7554A only For N-ch open-drain input/output selection The current flowing in built-in pull-up and pull-down resistors is excluded.
42
PD7554A, 7554A(A)
AC CHARACTERISTICS (Ta = -10 to +70 C, VDD = 2.0 to 3.3 V)Note1
Parameter Internal clock cycle time P00 event input frequency P00 input rise/fall time P00 input high/low level width SCK cycle time Symbol tCY fPO tPOR, tPOF tPOH, tPOL Input Output SCK high/low level width SI setup time (to SCK) SI hold time (to SCK) SCKSO output delay time INT0 high/low level width RESET high/low level width tKH, tKL tSIK tKSI tKSO tIOH, tIOL tRSH, tRSL CL = 100 pF 50 50 Input Output 3.3 13.4 16.6 6.7 8.3 500 500 3500
Note2
Test Conditions
MIN. 13.4 0
TYP.
MAX. 200 150 0.2
Unit
s
kHz
s s s s s s
ns ns ns
tKCY
s s
Note 1. PD7554A only 2. tCY = 2/fCC or 2/fC
AC Timing Test Point (Except CL1 Input)
0.85 VDD 0.15 VDD
Test Points
0.85 VDD 0.15 VDD
43
PD7554A, 7554A(A)
CHARACTERISTICS OF DATA MEMORY DATA RETENTION AT LOW SUPPLY VOLTAGE IN STOP MODE PD7554A : Ta = -10 to +70 C
PD7554A(A) : Ta = -40 to +85 C
Parameter Data retention supply voltage Data retention supply current Data retention high RESET input voltage RESET setup time RESET hold time Symbol VDDDR IDDDR VIHDR tSRS tHRS VDDDR = 2.0 V 0.9 VDDDR 0 0 Test Conditions MIN. 2.0 0.1 TYP. MAX. 6.0 5 VDDDR +0.2 Unit V
A
V
s s
Data Retention Timing
STOP
Operating Mode
Data Retention Mode
VDD
STOP Instruction Execution
2 1 3
2
RESET
4
4
tSRS
tHRS
1 2 3 4
VDDDR VIH1 VIHDR IL1
Caution In the data retention mode, every input must be below VDDDR.
44
PD7554A, 7554A(A)
Clock Timing
1/fC tCL tCH
CL1 Input
tCR
tCF
1/fP0 tPOL tPOH
P00 Input
tPOR
tPOF
Serial Transfer Timing
tKCY tKL tKH
SCK
tSIK
tKSI
SI
Input Data
tKSO
SO
Output Data
45
PD7554A, 7554A(A)
Test Input Timing
tIOL
tIOH
INT0
RESET Input Timing
tRSL
tRSH
RESET
46
PD7554A, 7554A(A)
fC vs. VDD Operating Guarantee Range PD7554A : Ta = -10 to +70 C PD7554A(A) : Ta = -40 to +85 C t1 t2 CL1
Clock Input Frequency fC [kHz]
7. CHARACTERISTIC CURVES
5
1000 500
1 2t2 1 t1t2 : fC =
100
Operating Guarantee Range
: PD7554A : PD7554A(A) 10 0 1 2 3 4 5 Supply Voltage VDD [V] 6
R vs. VDD Operating Guarantee Range PD7554A : Ta = -10 to +70 C PD7554A(A) : Ta = -40 to +85 C 500 Operating Guarantee Range
5
External Resistor R [k]
100 50 CL1 CL2 10 R
: PD7554A : PD7554A(A) 0 1 2 3 4 5 Supply Voltage VDD [V] 6
fP0 vs. VDD Operating Guarantee Range PD7554A : Ta = -10 to +70 C PD7554A(A) : Ta = -40 to +85 C t1 t2
P00 Event Input Frequency fP0 [kHz]
5
1000 500
1 2t2 1 t1t2 : fX =
100
Operating Guarantee Range
: PD7554A : PD7554A(A) 6
10
0
1
2 3 4 5 Supply Voltage VDD [V]
47
PD7554A, 7554A(A)
5
700
fCC vs. VDD Characteristics Example (Reference Value) (Ta=25C)
600
Clock Oscillation Frequency fCC [kHz]
500 R=56k 400
300
R=100k
200 R=240k 100
Note1
0
1
2
3 4 Supply Voltage VDD [V]
5
6
7
5
fCC vs. Ta Characteristics Example (Reference Value) 700
Note2
600
Clock Oscillation Frequency fCC [kHz]
R=56k, VDD=5.0V 500
400
300
R=100k, VDD=3.0V
200
100
R=240k, VDD=2.0V
Note1
0
-40
-25
25 50 -10 0 Ambient Temperature Ta [C]
70 75
85
Note 1. 2.
PD7554A only PD7554A only operates within this range
48
PD7554A, 7554A(A)
fCC vs. R Characteristics Example (Reference Value) (Ta=25C) 1000 800 600 400 VDD=5.0V
5
Clock Oscillation Frequency fCC [kHz]
200
VDD=2.5V
90 70 50 30 VDD=2.0V
Note
10 10
30
50
70 90
200
400
600 800 1000
External Resistor Value [k]
IDD vs. VDD Characteristic Example (Reference Value) 1000 500 R = 56 k Operation R = 100 k Operation R = 150 k Operation Supply Current IDD ( A) 100 50
R = 56 k, HALTNote R = 100 k, HALTNote R = 150 k, HALTNote
(Ta = 25 C)
10 CL1 R CL2
1 0 1 2 3 4 5 6 Supply Voltage VDD [V]
Note PD7554A only
49
PD7554A, 7554A(A)
IOL vs. VOL Characteristic Example (Port 8) (Reference Value) (Ta = 25 C) 30
Output Current Low IOL [mA]
25 VDD = 5 V 20 15 VDD = 3 V 10 VDD = 2.5 VNote 5 0
Caution The absolute maximum rating is 30 mA per pin.
0 1 2 3 4 5 6
Output Voltage Low VOL [V] IOL vs. VOL Characteristic Example (Port 10, 11) (Reference Value) (Ta = 25 C) 30
Output Current Low IOL [mA]
25 20 VDD = 5 V 15 10 5 0 VDD = 3 V VDD = 2.5 VNote
0
1
2
3
4
5
6
Caution The absolute maximum rating is 15 mA per pin. .
Output Voltage Low VOL [V] IOH vs. VOH Characteristic Example (Reference Value) (Ta = 25 C)
Output Current High IOH [mA]
-5 -4 -3 -2 VDD = 3 V -1 0 VDD = 2.5 VNote
VDD = 5 V
Caution The absolute maximum rating is -5 mA per pin.
6
0
1
2
3
4
5
VDD - VOH [V]
Note PD7554A only 50
PD7554A, 7554A(A)
8. PD7554A APPLIED CIRCUITS
(1) Tape counter (VTR, deck)
Mechanical Control Microcomputer PCL SCK SO SI PD75008 PD75108 etc. CL1 SCK SI SO P80
Tape Counter Microcomputer RESET P00/INT0 Count Pulse
PD7554A
P113 P100 ~ P112
UP/DOWN Signal
P81
P82
P83
Driver PA80C
7-Segment LED
(2) Remote control reception + key entry + LED display
Master Microcomputer PCL SCK SO SI
PD7554A
PCL SCK SO SI P113 CMOS Output P110 P111 P112 Driver PA80C
PD75008 PD75108 etc.
(Chip Selector Transfer Request)
RESET LED 12
Open-Drain Output
On-Chip Pull-Up Resistor Input
P80 P81 P82 P83 P100
Remote Control Signal
Amplifier Circuit
P00
P101 P102 P103 Key Input 4 x 4
PC2800AHA(MS) etc.
51
PD7554A, 7554A(A)
9. PACKAGE INFORMATION
DRAWINGS OF MASS-PRODUCTION PRODUCT PACKAGES (1/2)
5
Caution Dimentions of ES products are different from those of mass-production products. Refer to DRAWINGS OF ES PRODUCT PACKAGES (1/2).
52
PD7554A, 7554A(A)
DRAWINGS OF MASS-PRODUCTION PRODUCT PACKAGES (2/2)
20 PIN PLASTIC SOP (300 mil)
20 11 detail of lead end
1 A
10 H
G
P
I
J
F
K
E
C D
NOTE
N M
M
B
L
ITEM A B C D E F G H I J K L M N P
MILLIMETERS 13.00 MAX. 0.78 MAX. 1.27 (T.P.) 0.40 +0.10 -0.05 0.10.1 1.8 MAX. 1.55 7.70.3 5.6 1.1 0.20 +0.10 -0.05 0.60.2 0.12 0.10 3 +7 -3
INCHES 0.512 MAX. 0.031 MAX. 0.050 (T.P.) 0.016 +0.004 -0.003 0.0040.004 0.071 MAX. 0.061 0.3030.012 0.220 0.043 0.008 +0.004 -0.002 0.024 +0.008 -0.009 0.005 0.004 3 +7 -3
Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition.
P20GM-50-300B, C-4
Caution Dimentions and materials of ES products are different from those of mass-production products. Refer to DRAWINGS OF ES PRODUCT PACKAGES (2/2).
5
53
PD7554A, 7554A(A)
DRAWINGS OF ES PRODUCT PACKAGES (1/2) 20 PIN SHRINK DIP FOR ES (REFERENCE) (UNIT: mm)
54
PD7554A, 7554A(A)
DRAWINGS OF ES PRODUCT PACKAGES (2/2) 20 PIN CERAMIC SOP FOR ES (REFERENCE) (UNIT: mm)
55
PD7554A, 7554A(A)
10. RECOMMENDED PACKAGING PATTERN OF PLASTIC SOP (REFERENCE) (UNIT: mm)
7.62
0.51
1.27
* * *
This recommended pattern conforms to the General Rules for Integrated Citrcuit Outer Shape (IC-74-2) specified by the Electronic Industries Association of Japan (EIAJ). The above pattern dimensions are applicable to all the products designated as EIAJ flat DIP (mini flat) of "Form A 300 mil type". If there is any possibility of causing a solder bridge, adjust the width (0.76) of each pad while maintaining the same length (1.27).
56
0.76
1.27
PD7554A, 7554A(A)
11. RECOMMENDED SOLDERING CONDITIONS
Solder PD7554A on the following recommended conditions. For details of recommended soldering conditions, refer to the information document "Semiconductor device mounting technology manual" (IEI-1207). For details on the soldering method and soldering conditions other than the recommended conditions, call the NEC salesman. Table 11-1 Surface Mounting Type Soldering Conditions
5
PD7554AG-xxx : 20-pin plastic SOP (300 mil) PD7554AG(A)-xxx : 20-pin plastic SOP (300 mil)
Recommended Condition Symbol Infrared reflow Package peak temperature: 230 C, Duration: 30 sec. max. (at 210 C or above), Number of times: Once VPS Package peak temperature: 215 C, Duration: 40 sec. max. (at 200 C or above), Number of times: Once Wave soldering Solder bath temperature: 260 C or below, Duration: 10 sec. max., Number of times: once, Preparatory heating tempererature: 120 C max. (Package surface temperature) Pin part heating Pin temperature: 300 C or below, Duration: 3 sec. max. (per device side) -- WS60-00-1 VP15-00-1 IR30-00-1
Soldering Method
Soldering Conditions
Caution Use of more than one soldering method should be avoided (except in the case of pin part heating). Table 11-2 Insertion Type Soldering Conditions
PD7554ACS-xxx : 20-pin plastic shrink DIP (300 mil) PD7554ACS(A)-xxx : 20-pin plastic shrink DIP (300 mil)
Soldering Method Wave soldering (pin only) Pin part heating Soldering Conditions Solder bath temperatures: 260 C or below, Duration: 10 sec. max. Pin temperature: 300 C or below, Duration: 3 sec. max. (Per pin)
Caution Ensure that the application of wave soldering is limited to the pins and no solder touches the main unit directly.
57
5
58
APPENDIX A. COMPARISON BETWEEN SERIES PRODUCTS FUNCTIONS
Product Name Item RC Instruction cycle/ system clock (5 V) Outside Ceramic Instruction set ROM RAM Total Port 0 Port 8 I/O Ports Withstand voltage Port 10 and 11 Withstand voltage Timer/Event Counter Serial Interface Supply Voltage Range Package
PD7554
PD75P54
PD7554A PD7554A(A)
PD7564
PD75P64
- -
PD7564A
PD7564A(A)
4 s/500 kHz 2.86 s/700 kHz - 47 types (SET B) 1024 x 8 64 x 4 16 P00-P03 P80-P82, P83 (CL2) 12 V 9V P100-P103, P110-P113 12 V 9V 8 bits 4 channels 2.5-6.0 V 4.5-6.0 V 2.0-6.0 V 2.7-6.0 V 2.7-6.0 V 4.5-6.0 V 12 V 12 V
2.86 s/700 kHz
15
P80-P82 9V
- - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
9V
2.7-6.0 V
2.7-6.0 V
20-pin plastic shrink DIP 20-pin plastic SOP
PD7554A, 7554A(A)
PD7554A, 7554A(A)
APPENDIX B. DEVELOPMENT TOOLS
The following development tools are available for developing systems that use PD7554A. Language Processor
Ordering Code (Product Name)
Host Machine
OS MS-DOSTM (Ver.3.10 to Ver.5.00ANote) PC DOSTM (Ver. 3.1)
Supply Medium 3.5-inch 2HD 5-inch 2HD
S5A13AS7554 S5A10AS7554 S7B10AS7554
PD7550/7560 series absolute assembler
PC-9800 series
IBM PC/ATTM
5-inch 2HC
PROM Write Tools
Hardware
PG-1500
PROM programmer which allows programming of single-chip microcomputer with typical PROM of 256K to 4M bits by stand-alone or from a host machine by connecting the accessory board and optional programmer adapter.
PA-75P54CS
PD75P54/75P64 PROM programmer adapter. Used by connecting it to the PG-1500.
Connects the PG-1500 and host machine by serial and parallel interface and controls the PG-1500 on the host machine. Ordering Code (Product Name)
Software
Host Machine PG-1500 controller PC-9800 series
OS MS-DOS (Ver.3.10 to Ver.5.00ANote) PC DOS (Ver.3.1)
Supply Medium 3.5-inch 2HD 5-inch 2HD
S5A13PG1500 S5A10PG1500 S7B10PG1500
IBM PC/AT
5-inch 2HC
Note A task swap function is provided in Ver. 5.00/5.00A, but the task swap function cannot be used with this software. Remark Operation of the assembler and PG-1500 controller is only guaranteed on the host machines and OSs shown above.
59
PD7554A, 7554A(A)
Debugging Tools
EVAKIT-7500B Hardware
EVAKIT-7500B is an evaluation board that can be used for PD7500 series models. For PD7544A, EVAKIT-7500B and option board EV-7554A are combined and used for system development. EVAKIT-7500B can operate alone. EVAKIT-7500B has a built-in serial interface on the board, so it enables debugging when it is connected to a TTY, TYPUTER, or RS232-C console. EVAKIT-7500B works as is a real-time tracer and traces state of the program counter and output port in real time. EVAKIT-7500B has a built-in PROM writer and improves debugging efficiency considerably. EV-7554A is an adapter board which is connected to EVAKIT-7500B and evaluates PD7554A. SE-7554A is a simulation board that has the programs developed by EVAKIT-7500B. SE-7554A evaluates a system in place of PD7554A. EVAKIT-7500 Control Program connects EVAKIT-7500B and the host machine with RC-232-C and controls EVAKIT-7500B on the host machine. Ordering Code (Product Name)
EV-7554A
SE-7554A
Software
EVAKIT-7500 control program (EVAKIT controller)
Host Machine PC-9800 series
OS MS-DOS (Ver.3.10 to Ver.5.00ANote) PC DOS (Ver.3.1)
Supply Medium 3.5-inch 2HD 5-inch 2HD
S5A13EV7500-P01 S5A10EV7500-P01 S7B11EV7500-P01
IBM PC series
5-inch 2HC
Note A task swap function is provided in Ver. 5.00/5.00A, but the task swap function cannot be used with this software.
5
Caution It is not possible to internally mount a pull-up resistor in a port in the EVAKIT-7500B. When evaluating, arrange to have a pull-up resistor mounted in the user system. Remark Operation of the assembler and PG-1500 controller is only guaranteed on the host machines and OSs shown above.
60
PD7554A, 7554A(A)
APPENDIX C. RELATED DOCUMENTS
DOCUMENT RELATED TO DEVICE Document Name User's Manual Document No. IEU-1111D IF-1027G
5
PD7500-series Selection Guide
DOCUMENT RELATED TO DEVELOPMENT TOOL Document Name EVAKIT-7500B User's Manual Hardware EV-7554A User's Manual PG-1500 User's Manual Document No. EEU-1017C EEU-1034A EEU-1335B EEM-1006 EEM-1356 EEM-1049 EEU-1291B
PD7550, 7560-series Absolute Assembler User's Manual
Software EVAKIT-7500 Control Program User's Manual MS-DOS base PC DOS base PG-1500 Controller User's Manual
OTHER RELATED DOCUMENT Document Name Package Manual Semiconductor Device Mounting Technology Manual Quality Grade on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Static Electricity Discharge (ESD) Test Semiconductor Device Quality Guarantee Guide Microcomputer-Related Product Guide-Third Party Product Document No. IEI-1213 IEI-1207 IEI-1209A IEI-1203A IEI-1201 MEI-1202 Note
Remark These documents above are subject to change without notice. Be sure to use the latest document for designing. Note To be published.
61
PD7554A, 7554A(A)
[MEMO]
62
PD7554A, 7554A(A)
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be Semiconductor adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
63
PD7554A, 7554A(A)
[MEMO]
The application circuits and their parameters are for references only and are not intended for use in actual design-in's.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard : Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special : Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc.
M4 92.6
MS-DOS is a trademark of MicroSoft Corporation. PC DOS and PC/AT are trademarks of IBM Corporation.

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